· Daily Matrices
· DAC Pavilion Panels
· Business Day@DAC
· Search the Program

· Keynotes
· Papers
· Panels
· Special Sessions
· Monday Tutorial
· Friday Tutorials

· Intro to EDA
· Interoperability
· UML for SoC Design
· Women's Workshop

· Structured ASICs
· Power Minimization





WEDNESDAY, June 9, 2004, 10:30 AM - 12:00 PM | Room: 6A
TOPIC AREA:  NANOMETER ANALYSIS AND SIMULATION

   SESSION 21
  Statistical Timing Analysis
  Chair: Anirudh Devgan - IBM Corp., Austin, TX
  Organizers: Charlie Chung-Ping Chen, Sani R. Nassif

  This session presents several new approaches to statistical static timing analysis. The first paper describes an incremental statistical timing approach based on a block-based traversal of the timing graph. The second paper proposes a way to compute the bounds on the distribution of circuit delay for timing graphs with arbitrary delay correlations. The third paper proposes an alternative approach to block-based statistical timing computation.

    21.1   First-Order Incremental Block-Based Statistical Timing Analysis
  Speaker(s): Chandu Visweswariah - IBM Corp., Yorktown Heights, NY
  Author(s): Chandu Visweswariah - IBM Corp., Yorktown Heights, NY
Kaushik Ravindran - Univ. of California, Berkeley, CA
Kerim Kalafala - IBM Corp., Hopewell Junction, NY
Steven G. Walker - IBM Corp., Yorktown Heights, NY
Sambasivan Narayan - IBM Corp., Essex Junction, VT
    21.2Fast Statistical Timing Analysis with Arbitrary Delay Correlations
  Speaker(s): Michael Orshansky - Univ. of Texas, Austin, TX
  Author(s): Michael Orshansky - Univ. of Texas, Austin, TX
Arnab Bandyopadhyay - Univ. of Texas, Austin, TX
    21.3STAC: Statistical Timing Analysis with Correlation
  Speaker(s): Jiayong Le - Carnegie Mellon Univ., Pittsburgh, PA
  Author(s): Jiayong Le - Carnegie Mellon Univ., Pittsburgh, PA
Xin Li - Carnegie Mellon Univ., Pittsburgh, PA
Lawrence T. Pileggi - Carnegie Mellon Univ., Pittsburgh, PA